x86 & Arm Rival, RISC-V Architecture Ships 10 Billion Cores

Calista Redmond, CEO of RISC-V International, told Embedded World that there are currently ten billion RISC-V cores on the market.

The ARM RISC-V architecture shipped 10 billion cores, which would be larger than the x86 and Arm architecture for the future

RISC-V, pronounced as “risk five”, is an open standard instruction set architecture (ISA) provided under free open source licenses. The basic instruction set has naturally aligned fixed-length 32-bit instructions, and the ISA approves variable-length extensions, meaning each instruction can be any numerical length in 16-bit plots . The instruction set is available in 32-bit and 64-bit address space versions and is created for a wide range of uses. Various subassemblies support everything from tiny embedded systems and PCs to supercomputers with vector processors and warehouse-scale rack-mounted parallel computers.

Calista Redmond said open standards are key.

Linux does it for software, and we do it for hardware. We estimate that there are 10 billion RISC-V cores on the market.

But, the path to ten billion was no quick feat. It is reported that it took seventeen years of trial and error for the ARM architecture to reach the milestone in 2008. On the other hand, RISC-V only took twelve years to reach ten billion . Redmond predicts that the number of RISC-V processor cores will reach eighty billion by 2025.

Source: Embedded World 2022.

This news included the announcement of the approval of the four new specifications and extensions from this year. The four new specifications are:

  • The RISC-V specification for SBI architects a firmware layer between the hardware platform and the operating system kernel using a supervisor mode application binary interface (S mode or VS mode). This abstraction enables platform services common to all RISC-V operating system implementations. Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratifying the specification will ensure a standard approach across the entire RISC-V ecosystem, ensuring compatibility. The development and ratification of this specification was led by Atish Patra de Rivos, with work led by the platform’s horizontal steering committee.
  • RISC-V UEFI protocols integrate existing UEFI standards on RISC-V platforms. The development and ratification of this specification was led by Sunil VL, Ventana Micro, and Philipp Tomsich, VRULL GmbH, with work conducted within the Privileged Software Technical Working Group.
  • E-Trace for RISC-V defines a highly efficient approach to processor tracing that uses a branch trace, ideal for debugging any type of application, from tiny embedded designs to super powerful computers. The E-Trace documentation for RISC-V specifies the signals between the RISC-V core and the encoder (or input port), a compressed branch tracing algorithm, and a packet format to encapsulate the trace information. compressed branch. The development and ratification of this specification was led by Gajinder Panesar of Picocom and the E-Trace working group of RISC-V.
  • RISC-V Zmmul Multiply Only allows low cost implementations that require multiply but not divide operations and is part of the RISC-V Unprivileged specification. The development and ratification of this extension was led by Allen Baum, with work conducted within the unprivileged ISA committee.

Sources of information: IT reception, RISV.org

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